1. Field of the Invention
The present invention relates to a package substrate, a package structure having the package substrate, and a method of fabricating the same, and, more particularly, to a package substrate without a core layer, and a package structure having the package substrate.
2. Description of Related Art
With the rapid growth in the electronic industry, high-end electronic products have been developed to have a compact size and a low profile, and to be highly integrated. As the packaging technology advances, an increasing number of different types of chip packaging technologies have been developed, and the size of the semiconductor package is continuously decreasing, in order to achieve the low-profile requirement for the semiconductor package.
A typical packaging substrate structure is formed by stacking copper layers and insulating layers. FIG. 1 is a cross-sectional view showing a conventional package structure.
The conventional package structure comprises: a core layer 10; a first wiring layer 11 and a second wiring layer 13 formed on the core layer 10; conductive vias 15 penetrating the core layer 10 for electrically connecting the first wiring layer 11 and the second wiring layer 13; a first insulating layer 12 and a second insulating layer 14 formed on the first wiring layer 11 and the second wiring layer 13, respectively, with a portion of the first wiring layer 11 and the second wiring layer 13 exposed; and a semiconductor component 31 having bonding pads 310 for electrically connecting with the first wiring layer 11.
However, a package substrate 1 (which comprises a first wiring layer 11, a first insulating layer 12, a second wiring layer 13, a second insulating layer 14, and conductive vias 15) used in the conventional package structure typically has at least two wiring layers that are electrically connected to each other via the conductive vias 15.
However, the conductive vias 15 are fabricated through a mechanical drilling or a laser drilling process to form through holes penetrating the core layer 10, followed by an electroplating process to form an electroplated copper layer in the through holes. This undesirably increases the complexity of the fabricating processes.
In addition, the package substrate 1 used in the conventional package structure has a core layer. After the conductive vias in the core layer are formed, a buildup wiring layer is formed on the top and bottom surfaces of the core layer. Generally speaking, the core layer has at least two wiring layers. Since the substrate thickness cannot be reduced, it is difficult to reduce the overall thickness of the package structure.
Accordingly, with the increased demands for miniaturization of the electronic products as well as the low-profile substrate, there is an urgent need for reducing the substrate thickness such that the overall thickness of the package structure is reduced.